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Background

Microfabrication

Accordingto Fransilla, microfabrication is the process of making of veryminute structures having measurements of a micrometer in size andeven smaller. It is used today in many different fields ranging frommechanical, biological and material science. (ix). MEMS(michroelectromechanical systems), michro machines, micro fluidics,solar cells, flat panel displays and power MEMS are some of thosescientific applications of Microfabrication discipline.

Inthe building of Microsystems, different materials are used. Theyrange from silicon, glass, ceramics, boron, quartz and metals e. t.c. The aspects of these materials are also carefully looked into thatinclude the shape, electrical properties, surface properties, opticalproperties and chemical properties.

Microfabricationas a practice however, involves various technologies to come up witha final working result. These technologies are to start with:lithography, etching and cleaning, and deposition of materials. Here,wet etching, dry etching, CVD (chemical vapor deposition), PECVD(Plasma Enhanced Chemical Vapor Deposition), sputtering are involved.Secondly, mechanical michromachining is also a microfabricationtechnology and thirdly, laser ablation. The performance andfunctionality of final devices fabricated are sensitive to many ofthe parameters properties that are a product of each step. Forspecial application and rapid prototyping there exists a wide varietyof production technologies and materials. These are generally do notgo well with mass production.

Inthis study, we will concentrate more on the first technology as usedin the field of electronics. And as a process, microfabricationinvolves various techniques. In each technique, there are steps thatare carried out and have been elaborated well in this document. Onthe same note, since the practice deals with minute measurements(micrometer and below), care is taken to ensure that each step isthoroughly and effectively measured. Consequently, measurements,calculations and use of models are applied to produce a precise andauthentic result.

Diffusion

Inelectronics, doping is a method extensively applied in theconstruction of semiconductors, where n-type and p-type elements arebrought together to create “holes” where electrons will passthrough and allow for electrical conduction. More precisely, then-type usually has an extra valence electron and releases thiselectron in the lattice and by so doing creates a surplus ofelectrons over holes. i.e. (n&gtp). The p-type on the contrary is animpurity with less valence electron which creates a vacant state inthe valence band therefore creating a surplus of holes overelectrons. i.e. (p&gtn).

SAGKOL(02) notes that doping is adding impurities in a semi-conductor in awell controlled manner to change its electrical properties. Forexample, in the making of semi-conductors, silicon which in itspurest form is an insulator is doped with an oxide layer (conductor)in the production of CMOS.

Diffusionis a process used to dope impurities into a semiconductor byintroducing them to the surface of the doped material. (SAGKOL 5). Asa principle, diffusion stipulates that particles move (diffuse) froma higher concentration to lower concentration. In our case, thedifference in their concentration causes dopants to literally diffuseboth vertically and laterally from the higher concentration ofdopants to the lower. (See fig a). Notably, although it can becorrectly said that diffusion takes place at all temperatures, thediffusivity has an exponential dependence on T.

Figa. doping by diffusion

Nowadays,diffusion is used to achieve various tasks in micro fabrication. Theyinclude: To obtain steep profiles after ion implantation due toconcentration dependent diffusion, to redistribute dopantshomogeneously in poly silicon layers or to drive-in dopants forwells, for deep p-n junctions in power semiconductors. Also, it isused to denude near surface layer for oxygen to nucleate and to growoxygen precipitates. Finally, it is used to get rid of undesiredimpurities.

Indiffusion, predisposition is used. It helps in providing a controlledamount of dopants. Here, a furnace-tube system using dopant sourcesof solid, liquid or gaseous state is applied. However, the process isnot absolutely reliable as it only gives 10% uniformity. Boronpredisposition is a good example, and for better uniformity, solidstate is used.

B2H6+ 3O2→3H2O+ B2O3

Si+ O2→SiO2

Thisremains the preferred method of introducing dopants into transistordevices.

Agraph can be used to show this effect.

Dopantsmove from points of higher concentration to points of lowerconcentration with flux J in the graph. Here, N (x,t) is the functiontime.

Thisis called as Fick’s 1stlaw of diffusion.

Where:D is the diffusion coefficient.

J(x, t) is the flux and measured in units per cm2.s i.e. #/ cm2.s.

Acontinued equation for the particle flux can be as follows:

Wherethe is the rate of increase of concentration with time.

And–D. J is the negative of divergence of particle flux.

Theoriginal surface concentration, N0,can be determined by the solid solubility of Boron at the depositiontemperature, 8500C.The final surface concentration and Junction depth are then given by:

Let’swork out an example to show how the measurements are done.

Question:A p-type (boron) diffusion is performed in silicon as follows for 30minutes at 9000C.What is the deposited Q? Assume that the solid solubility ismaintained at the surface (x=0).

Solution:according to figures above, the boron diffusion coefficient is:

At9000C:

Thedeposition is performed at 9000Cwhere the boron solid solubility is Cs= 1.2 x 1020cm-3.The dose introduced is then:

Oxidation

Infabrication of CMOS (complementary metal-oxide-transistors) devices,after diffusion is done, wet oxidation becomes the second step. It isperformed on test and device wafers. This wet oxidation grows a fieldoxide on the surface of the wafer in order. Before this is donethorough standard cleaning is done.

Duringthe first standard clean the furnace is turned on and ramped up to anintermediate temperature of 800° C. However, to ensure the bestwafer results, this standard clean needs to be performed immediately,prior to high- temperature processing. Any contaminants (organic or ionic) residing on the surface of the wafers will be removed duringthe standard clean, creating a suitable growth surface for the oxide.The standard clean bench involves four tabs: SC 1, SC 2, HF and acascade rinse of de-ionized water. For the removal of any organiccontaminants, the wafers are submerged in the SC 1 tub with asolution of ammonium hydroxide and DI water. The HF tub (hydrofluorictub) is used to submerge the wafers so that the thin layer of oxideformed in the SC 1 tub clean can be removed.

Wafersare then loaded at the center of the furnace contained in a coldquartz wafer boat. The bubbler is turned on, introducing water vaporfor a 16.25 minute wet oxidation. Wet oxidation, having faster timesof oxidation is preferred than dry oxidation.

Insputtering, argon atoms are ionized at low pressure by an electricfield. The positive ions are accelerated towards the negativelycharged target. Then, sputtering material condenses on the ambientsurfaces. In sputtering etching, real etching occurs by physicalknocking of the wafer. It is highly anisotropic, has poor selectivityand to a disadvantage, metals can be used as a barrier material toprotect the wafer.

Photolithography

Lithographyconsists of patterning substrates by employing the interaction ofbeams of photons or particles with materials. A photolithographysystem consists of a light system, a mask, and an optical projectionsystem. Photolithography is a well-studied method of patterningsomething basic like a simple low resolution pattern to somethingcomplex like an intricately small pattern of metal onto substratessuch as silicon, as used in the semiconductor industry, or glass inmicrofluidic devices. Masks are used to generate the pattern desired.They are found in two polarities, dark and light field (or alsocalled positive and negative masks). The method of patterning thesubstrate differs and may take form as hard or soft. In the former,masks make physical contact with substrate while in the latter theyjust hover slightly above the image and project an image. Anotherform is proximity printing which is seen as a compromise betweencontact printing and projection printing. A photomask is a glassplate with a patterned emulsion or metal film on one side.

Photoresists areviscous liquids made up of an organic polymer, a sensitizer, and acasting solvent, and are sensitive to light like film in cameras.They are very essential in lithography for they allow for the imageformation on the substrate. They come in two forms: positive andnegative resists. Positive resists are made soluble to developers bya process called chain scission in which the bonds break when theyare exposed to DUV (Direct Ultra Violet) light (~220-240nmwavelength). However, the negative ones react in an opposite way inthat they are rendered insoluble after exposure to light, making itmore stable. The initial step is to distribute the thin layer evenlyonto the cleaned substrate by using what is called a photoresistspinner. The following equation governs the thickness of layer (T) ofphotoresist:

WhereT= Thickness of the layer.

K=CalibrationConstant.

C=Polymer concentration in g/100mL solution (measure of molecularweight)

ŋ=Instrinsic velocity.

ω=Rotations per minute (RPM).

Etchingand Cleaning

Asmentioned in photolithography, etching is the selective removal ofmaterials. There are two different categories of etching: Wet and dryetching. Wet etching involves use of chemicals in liquid state whiledry etching uses gas phase chemistry. These both methods can beisotropic or anisotropic. Isotropic means that they provide the sameetch rate in all directions while anisotropic provide different etchrates in different directions. The following is an equation to showthe reaction.

Si+2H+⎯⎯→Si2++ H2

SiCln(absorbed)⎯→SiCln(gas)

Usually,wet etching is isotropic. However there exists an important exceptionof anisotropic silicon wet etching. Here, liquid chemicals are usedof alkaline solutions like potassium hydroxide (KOH). Wet etchingtypically provides a better etch selectivity for the material to beetched in comparison with neighboring other materials. For instance,acid-based hydrofluoric acid chemistries are used in wet etching ofsilicon (iv) oxide. SiO2isisotropically etched in dilute hydrofluoric acid, or BOE (BufferedOxide Etch). In BOE, typical etch rates for high quality (thermalgrown) Silicon (iv) Oxide films are 0.1µm/minute. Typically, BOEetches silicon (iv) oxide much fast than it etches Silicon andphotoresist. The rate of etching is normally dependent on a number offactors that include: temperature, type of oxide and concentration ofimpurities. In this case, if there is high concentration ofphosphorus in the oxide it is fast and slow if it has a highconcentration of Boron.

Onthe other hand, dry etching that results in a better pattern transferis often anisotropic in nature, as mask under etching is avoided.(See Fig. b below). Dry etching has three methods including: plasmaetching, sputtering and Reactive Ion Etching. In the microelectronicsindustry, RIE (reactive ion etching) of thin films is very commonexample of dry etching. Plasma etching involves using gaseous plasmacreated by RF excitation. The RF power source is usually at afrequency of 13.56 MHz. The plasma contains fluorine or chlorine ionswhich etch Silicon (iv) oxide. Moreover reactive ions are generatedin plasma and are accelerated towards the surface to be etched, thusproviding directional etching characteristics.

Inthe Reactive Ion Etching (RIE), a combination of plasma etching andsputtering etching is used. Here, plasma systems are used to ionizereactive gases. They are then accelerated to bombard the surface.Finally, etching occurs by impulsive force or the momentum transferand chemical reaction.

Figb. Schematic of isotropic and anisotropic thin-film etching

MetalEvaporation

Thelast process used in building the CMOS devices is a metal evaporationprocess called Physical Vapor Deposition (PVD). In this process, themetal to be evaporated is placed inside an element. The filament isheated to the metal’s boiling point under a vacuum where itcondenses to the wafer suspended above the filament.

Thewafer is flat in shape in contrast to the evaporating metal fluxwhich is spherical. Therefore, the metal film formed is thicker atthe center than at the edges. In calculating this, two methods areused. First method: determine the volume of the metal mass beingevaporated. By comparing this to the surface area of the sphere at adistance, the thickness at a particular point can be calculated. Thisis a lesser accurate method reason being it assumes that metalspreads out uniformly on the wafer. Second method: a formula is usedas in below.

Here,the growth rate at the edge is compared to the growth rate at thecenter of the wafer. ‘m’ is density, ‘p’ is the massevaporation rate, ‘θ’ is the angle of the substrate relative tothe vapor stream, and ‘Φ’ is the angle measured from the normalto the plane of the source.

Fabricationsequence

Thefabrication sequence starts with a silicon wafer of blank p-type anda layer of oxide is formed. Using photolithography, a pattern is madeonto it to form a mask for the N-well and the N-type transistor. Inthis case, the dopant used is phosphorus, and the oxide is removed.The drive-in step is performed to finish the N-well.

Formingthe source and the drain of the PMOS transistor is the next step.During the drive-in step of the N-well, an oxide is grown. This nowis used to pattern form the masks for these parts. To create N+(higher concentration then N) regions, phosphorus diffusion iscarried out. To form now the source and drain of the transistor,stripping the oxide and performing a drive-in step is done. The P+drain and source for the NMOS transistor is done in the same manner.

Thedrive-in step of the P+ regions also forms the oxidation necessary tomask the contact vias. Patterning of this oxidation is accomplishedthrough photolithography and etching. Lastly through PVD (PhysicalVapor Deposition), aluminum is deposited. Through the same steps thatoxide is patterned, this aluminum is patterned and etched to form thecontact pads.

Inanother perspective, microfabrication processes of CMOS devices arerequired for today’s and tomorrow’s microprocessors, ICs and veryminute electronic components that comprise of tens of millions oftransistors on a single relatively small chip. For instance, usingIBM’s 90nm technology, Apple computer’s 64 bit power PC – G5processor was made. It had more than 58 million transistors.

Nevertheless,to achieve such great VLS (very large scale) integration, indesigning the CMOS-based MEMs or even micro systems, the designer toa great extent must adhere to the chosen sequence of CMOS process.Otherwise, the functionality of the chip-on electronics will besacrificed.

Ina summary, there are four micro fabrication techniques that form thebasis for the fabrication of Integrated Circuits (ICs) using CMOS orBiCMOS technology. These are: deposition, patterning, doping andetching. These techniques are combined to for instance create an IClayer by layer. An insulating layer such as a silicon (iv) oxide thinfilm is deposited on the substrate, usually a silicon wafer. On topof it, a light sensitive photoresist layer is deposited and afterthat, photolithography is used to pattern it using UV lightradiation. At the end, the pattern must be transferred from thephotoresist layer to the silicon (iv) oxide layer. This isaccomplished by an etching process. The remaining photoresist (whichwas not part of the pattern) is then removed. The removal is by usinghydrofluoric acid. Also, two techniques are used to remove thisphotoresist: using liquid resist strippers that make the resist swelland lose adhesion to the substrate. Secondly, dry processing is doneby oxidizing (burning) the resist in an oxygen plasma system. Theprocess is commonly referred to as resist ashing. The next layer (aninsulating thin film) is deposited and structured and so on.

Thepreparation of the IC has now to include the doping. Up to now, nodoping has been done. However, the wafer is ready for doping. Thewafer is exposed to the dopant and this is dependent on the desiredoutcome for instance, whether it is an n- type or p- type component.Usually, the n-type feature is doped in the p- type siliconsubstrate. The principle of diffusion plays part here i.e. particlesdiffuse from regions of higher concentration to lower concentrationand the result is the dopant placed in the substrate within giventime. Yet, the oxide layer (Silicon (iv) oxide) is still in place.The step for getting rid of it is redone, again by use ofhydrofluoric acid. Lastly, the feature is successfully created and isnow ready for testing.

Inthe sequence it has to be noted that the photeresist layer comes inpositive or negative layer. For the negative one, it is only capableof producing features down to about 2.0 µm. contrary, the positivephotoresist layer is capable of producing even smaller sizes ofdevice features which are typically below 1.0 µm but may be as smallas 0.15 µm. For that reason, today, most semiconductor and CMOStechnologies use the positive resist.

Thesedifferences in the photoresists arise from their developers and rinsechemicals or agents. For example, the positive resist’s developeris Sodium Hydroxide (NaOH) and tetra methyl ammonium hydroxide(TMAH). Its rinse chemical is water (H2O).The negative resist’s developer is xylene and Stoddard solventwhile its rinse agent is n- butylacetate.

Analysis

OxideCalculations

Thefollowing is an example of a task requiring oxidation calculations.

Considera chunk of silicon, where the left half has a (10) surface and theright half has a (11) surface. A wet oxidation is performed at 1050°C for 1 hour. What is the step height between the oxides over the(10) and (11) surfaces? Oxide thicknesses must be calculated usingthe Deal-Grove model.

T= 10500 C= 1323K → kT = 0.114 eV

B(10)and (11)= (386 µm2/ hr) *exp(-0.78eV / 0.114 eV) = 0.412 µm2/ hr

B/A(10)= (9.7 x 107µm/hr) * exp (-2.05eV/ 0.114eV) = 1.503 µm/hr

B/ A (11) = (1.63 x 108µm/hr) * exp (-2.05eV/0.114eV) = 2.526 µm/hr

A(10)= B/ [B/A] = 0.274 µm

A(11)0.163 µm

Xi= 0 → tau = 0

Xox,(10)= 0.5* (0.274)* [√(1+4* 0.412/(0,2742))- 1] = 0.519 µm

Xox,(11)= 0.5* (0.163)* [√(1+4* 0.412/(0.1632))- 1] = 0.566 µm

Xsi,(10)= 0.46* Xox,(10)= 0.239 µm

Xsi,(11)= 0.26 µm

Stepheight = (Xox,(11)– Xsi,(11))– (Xox,(10)– Xsi,(10))= 0.026 µm

MetalThickness Calculations

Thefollowing is an example of a task requiring metal thicknesscalculations.

Anarbitrary material is deposited on a silicon wafer at a thickness of100 nm. It is then patterned with photoresist (assume 90 degreephotoresist sidewall angles) and etched. What is the etch isotropicfactor if the sidewall angle is:

  1. 45 degrees

  2. 60 degrees

  3. 89 degrees

  4. For parts (a) to (c), calculate the width at the top of the etched feature if the photoresist is patterned at a width of 200 nm.

Solution

  1. A f = 1-r lat/r ver

rlat/rver= 1/[tan(450)]= r lat/rver=1

Af =0

  1. Af = 1-(1/[tan(600)]) = 0.423

  2. Af = 1- (1/[tan (890)]) = 0.983

  3. Wtop = W – 2 * thickness (r lat/r ver)

450→Wtop= 0nm

600→Wtop= 84.6 nm

890→Wtop= 196.51 nm

AluminiumResistance

SheetResistance

R

R = V / I

esistance in electronics is a measurement testing theopposition to the passage of electrical current. If the resistance ofa conductor is high this means that it allows a small amount ofcurrent to flow for the voltage applied. It is dependent on a varietyof factors that range from the thickness of the conductor, voltageapplied and the amount of current flowing in the circuit. It is givenby the formula:

Sheetresistance on the other hand is the measurement of resistivity ofthin films that have a uniform thickness. It is measured in ῼ /□.What if we are measuring the sheet resistance of a square area? Then,L = W and Rs= p / t

Ris the resistance of the object, measured in ohms.

Pis the resistivity, a constant with a unique value for everyelectrically conducting element.

tis the thickness of the film, or sheet thickness.

Lis the length of the object through which the current is beingpassed.

Wis the width of the object, in our case, it cancels out with thelength.

DiffusionCalculations

Toproduce CMOS devices, three diffusions were necessary. An N-welldiffusion was made to create the N-type tub in which the NMOStransistor was built. Secondly, N+ regions were created in the P-typesubstrate to form the source and drain of the PMOS transistor.Lastly, the final diffusion formed P+ regions in the N-type tub tocreate the source and drain of the NMOS transistor. The followingtable shows deposition depth and resistance shows the calculateddepth of these diffusions and the final sheet resistances.

Deposition step

Junction Depth (cm)

Resistance (ohm/sq)

N-well

1.751 x 10-06

1.7704

N+

1.301 x 10-05

307.45

P+

7.505 x 10-05

99.933

Thejunction depth was calculated by setting the diffusion concentrationto the background concentration and solving for the depth.

N(x,t)= NB=1.00 x 1015cm-3

Fora constant source diffusion, this results in:

Xj= 2√Dt erfc-1(NB/NO)

Note:erfc stands for complementary error function.

Andfor limited source diffusion:

Xj= 2√Dt In (NO/NB)

Thefinal sheet resistance is calculated using the Irvin’s curves.Irvin’s curves are used to determine the average conductivity (p)for diffused layers given 2 or three of the following parameters:

  1. Ns (Surface Concentration)

  2. X/Xj (for buried layers)

  3. Average conductivity

Thecurves are sorted by diffusion profile (either erfcor Gaussian),type (nor p),and background doping concentration (Nc).The following is an example of an Irvin’s curve. The x-axis showsthe RxSjproduct and the y-axis shows the dopant calculation. The sheetresistance can be graphically solved for so long as the surfaceresistance, background resistance and junction depth are known. Thisis an n-type Gaussian Irvin’s curve. (See fig c below)

FigC. N-Type Gaussian Irvin’s Curve.

Irvin’scurves also apply in the p-type diffused layers. The following is ap-type Gaussian Irvin’s Curve. (see fig d below).

FigD. P-type Gaussian Irvin’s curve.

Processcharacterization measurements

Appropriatemeasures were taken during a lab session. In doing this, resistivitymeasurements were taken with the four point probe and by using ananospectrometer, oxide thickness measurements were performed.

SheetResistivity

Followingeach diffusion, the resistivity was measured in the correspondingtest regions. The following table shows data for the four point probemeasurements. All measurements are ohms per square.

Deposition

N-well

N+

P+

N-well

69.19

N+

70.36

14.35

P+2

261.5

2.822

494.5

Itis very important to remember that depositions were performed afteran oxidation growth. Following the deposition, an etch was grownhowever, the cause of the extra-high resistivity readings for then-well and p+ test regions could be by some oxide remaining on thewafer.

Oxidethickness measurements

Thethickness was measured afterwards for both wet and dry oxidations.These measurements are compared to the calculated values provided intable E: oxidation thickness measurements.

Becausethe wafer was placed into the furnace before it was at temperature,an error arose from the calculated oxidation thickness and theaveraged measurements.

Step

Calculated

Thickness (µm)

Measurement thickness (µm)

Error %

N-Well mask

0.76

0.7122

6.3

N+ Mask

0.51

0.4314

15

P+ Mask

0.66

0.5022

24

Field Oxide

0.62

0.5524

11

Gate Oxide

0.09

0.1001

11

FigE.Oxidation Thickness measurement

Inthis lab, the furnace was flushed with nitrogen until approximately4000C.This halted the oxidation process until it was removed and thechamber was flushed with oxygen. The error that arose after comparingwith the measured value was because oxygen was introduced at 400oCinstead of 1000oC to 1050oC, the linear and parabolic coefficientscalculated with the Arrhenius Rate Equation changed with time andskewed the calculations.

Resistorplots

Thereis a linear relationship of the direct relationship betweenresistivity and the resistance of a resistor made through the microfabrication process. It goes as this:

R= (Nsq)(Ps)+ (Rc)

Where:Nsqisthe number of squares.

Psisthe sheet resistivity.

Rc&shyis any contact resistance.

FigF below is a manifestation of the linear relationship between sheetresistivity and resistance.

FigF. Linear relationship between sheet resistivity and resistance.

Thisrelationship shown is for the N+ aluminum resistors assuming nocontact resistance. Although both are linear, aluminum has a lowerresistance the n+ region to be expected. Measurements were taken forthe actual resistance of each resistor in a die. They are provided infig G. (below).

FigG. Aluminum trace resistance.

Inthese characterizations, it is notable that Rc (contactresistance) is present this is evident by the non-zero, y-axis linecrossing. This contact resistance is caused by contact pads and viasnot being of the same doping or material as the resistors and beingcomposed of multiple squares.

Comparingwith bulk

Thereare basic characteristics that make thin films different from bulk.Due to the smallness of the thickness, surface effects like thesurface scattering of electrons are prominent. This leads to sizedependent resistivity.

Whencompared, the density of thin films is usually very small from thatof bulk materials. For instance, sputtered tungsten film can have adensity as low as 12 g/cm3compared with bulk value of 19.5 g/cm3.In the manufacture of the thin films, they should be pore-free. Poresabsorb water vapor and due to their high surface area, they turnreactive. Such films oxidize and corrode easily. This leads to longterm instability of the thin films. Many other thin film properties,dielectric constant, coefficient of thermal expansion and refractiveindex are also thickness dependent.

Thinfilms can be either amorphous, single crystalline (epitaxial) orpolycrystalline as deposited. Epitaxial films during annealing remainsingle crystalline. Polycrystalline films go through grain growth andsometimes phase transitions into other crystal structures. Amorphousfilms either crystallize or stay amorphous. In crystallizing, theychange into a polycrystalline material and in some very specialconditions, the change to single crystalline material. Silicondioxide, silicon nitride and aluminum oxide are exceptional amorphousfilms because they remain amorphous in all typical micro fabricationprocesses.

Whendifferent sputtering systems are used to make films, the filmsdiffer. To even a larger extent, two films prepared by completelydifferent deposition processes will differ.

DeviceTesting

Resistortesting is done by sweeping a voltage over them, and measuring thecurrent (that is all resistors on a single die). For instance, thefig below (Fig H) shows test resistors.

FigH. Test Resistors.

Thismask shows resistors included in the mask set. All of them are 80µmlong and 40µm wide. There are contacts at the two ends, 20 squaresapart. For two out of three resistors, there is an additional contact5 squares away from one end. To estimate the contact resistance, thethird can be used. The three different test resistors involved are asfollows:

  1. p – Resistor: It is used to measure the sheet resistivity in ohms/square of p-type region (Boron diffusion).

  2. n+/p resistor: It is used to measure the sheet resistivity in ohms/square of n-type region (Phosphorus Diffusion) in the p-well.

  3. Internal Base resistance.

Thefollowing are examples of graphs of an actual measurement taken ofresistors with their dimensions.

FigI. Aluminum Resistor measurement.

FigJ. N+Resistormeasurement.

FigK. P+Resistor measurement.

FigL. N-well resistor measurements

Diodes

Throughthe single and double diffusion process, both n-type and p-typediodes of four different types were fabricated. And as it was donewith the resistors, a voltage was swept over the contacts and thecurrents were monitored. The figure below (fig M) shows the results.

FigM. Diode measurements.

Effectsof Series Resistance

Thesingle diffusion diode (Fig M) had a large contact resistance on thepads and this made the exponential growth to be very shallow (fromthe graph). The resistance measurements show that this contactresistance is from approximately 35 to 200 ohms.Thesingle diffusion diodes have a model, which is a diode surrounded bytwo resistors in series. By introducing this resistance, the currentis limited causing the limited growth.

Transistors

Boththe NMOS (Negative-channel Metal-Oxide Semi-conductor) and PMOS(Positive Channel MOS) types of transistors were made in differingsizes, through fabrication. Testing of the transistors wasaccomplished by sweeping a primary voltage across the drain andsource (VDS)a second voltage across the gate and the source. (VGS).

Inverters

Inmaking inverters, both NMOS and PMOS devices are brought together.The process takes an advantage of benefiting from the strengths ofboth. In fig N, a ratio of 1:3 of NMOS as to PMOS channel was used tomake an inverter.

FigN. Layout of inverter with 3 parallel channels for PMOS and 1 channelfor NMOS

Results

Inthe course of making the devices, different methods were employed.Consequently, they gave functioning and non functioning devices.Notably, all functioning devices only required one diffusion and arethe resistors and single diffusion diodes. On the other hand, allmalfunctioning devices were multiple devices that include thetransistors and double diffusion diodes.

FailureAnalysis

FigO below shows the CMOS transistor measurements. This was aftertesting a faulty diode, which was a double diffusion diode.

FigO. CMOS Transistor Measurements.

Fromthese results, a conclusion is inferred that the double diffusiondiodes are acting as resistors. It is observed that from the graph,the double diffusion case, its I-V characteristics is linear until ithits an upper current rail. The explanation for this is the oxidethat remains on wafer until the time of resistance measurements. Withsome oxide being in the areas of diffusion, the dopants were trappedin the oxide and detached during the etching process. Chances ofthere being a PN junction were done away with when this trappingresulted in the two contacts for the diode being located in the samelevel of doping.

Boththe NMOS and PMOS transistors were faulty. The faulty NMOS device hasa linear section of the I-V characteristic that turns exponentialbefore railing out. Other observations can be made about transistorsfrom fig O (above), and precisely on the figure on the right. Atvoltages less than 10VDS,the device is acting as a resistor. However, at voltages more than10Vds,the device acts as a diode. This phenomenon can be made explicit byexcess oxide remaining at the source and the drain regions and thecontact pads.

Theresistance of the diode is adding series resistant to the resistanceof the transistor at low voltages. Similar to the faulty diodes, theI-V characteristics are made to be nearly linear. However, the oxidestarts to break down at voltages (drain source) above 10 volts.Thiscauses a decrease in resistance and the increase of the slope of theI-V curve. When we consider the I-V characteristics of the PMOS, theystay nearly linear for the same reason. Nevertheless, the oxide layernever reaches a break down point.

Recommendations

Itis very conspicuous that the oxide that remains on the wafer at thetime of diffusion or deposition brings undesired results in devices.In a more real sense, multiple diffusion devices can be made to workby enabling enhancements in the process as it has been seen thatsingle diffusion devices worked. In the consideration of doublediffusion devices, both diodes and transistors, it can be explainedthat their failure is out of the oxide layer that was etched (thediode) and thus losing the dopants. In transistors, this oxide layerwas between the source, drain and contact pads.

Thewafer and BOE (Buffered Oxide Etch) should be considered in fixingthis problem. To start with, the wafer should have been left in theBOE for at least a longer time and secondly, throughout the durationfabrication process, the BOE was never replaced. Although it is abuffered etch, it is sure to lose strength over time. Hence, infuture processes, let us replace the BOE etch at least once.

Moreover,the laboratory processes of observing the procedures of fabricationshould continue to be more vigilant on the oxide layer as we haveseen earlier that it arises a lot of discrepancies. They should studywhat chemical, electrical or perhaps mechanical methods can be coinedin a bid to settle this oxide-layer issue.

References

Fransillla,sami. IntroductionTo Micro fabrication.John Wiley &amp Sons Ltd, The Atrium, Southern Gate, Chichester,West Sussex, PO19 8SQ: United Kingdom. 2010. Print.

SAGKOL,Assist. Prof. Dr. Huseyin. “Department of Electrical andElectronics Engineering: Doping”. EEE496 MICRO FABRICATION Dopingn. d: n. pag. Web. 2ndDec 2014.